//
//#ifndef __SIMPLE_DMA_H_
//#define __SIMPLE_DMA_H_
//
///******************************************************************************
//*
//* Copyright (C) 2010 - 2019 Xilinx, Inc.  All rights reserved.
//*
//* Permission is hereby granted, free of charge, to any person obtaining a copy
//* of this software and associated documentation files (the "Software"), to deal
//* in the Software without restriction, including without limitation the rights
//* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
//* copies of the Software, and to permit persons to whom the Software is
//* furnished to do so, subject to the following conditions:
//*
//* The above copyright notice and this permission notice shall be included in
//* all copies or substantial portions of the Software.
//*
//* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
//* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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//* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
//* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
//* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
//* SOFTWARE.
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//* in advertising or otherwise to promote the sale, use or other dealings in
//* this Software without prior written authorization from Xilinx.
//*
//******************************************************************************/
///*****************************************************************************/
///**
// *
// * @file xaxidma_example_simple_intr.c
// *
// * This file demonstrates how to use the xaxidma driver on the Xilinx AXI
// * DMA core (AXIDMA) to transfer packets.in interrupt mode when the AXIDMA core
// * is configured in simple mode
// *
// * This code assumes a loopback hardware widget is connected to the AXI DMA
// * core for data packet loopback.
// *
// * To see the debug print, you need a Uart16550 or uartlite in your system,
// * and please set "-DDEBUG" in your compiler options. You need to rebuild your
// * software executable.
// *
// * Make sure that MEMORY_BASE is defined properly as per the HW system. The
// * h/w system built in Area mode has a maximum DDR memory limit of 64MB. In
// * throughput mode, it is 512MB.  These limits are need to ensured for
// * proper operation of this code.
// *
// *
// * <pre>
// * MODIFICATION HISTORY:
// *
// * Ver   Who  Date     Changes
// * ----- ---- -------- -------------------------------------------------------
// * 4.00a rkv  02/22/11 New example created for simple DMA, this example is for
// *       	       simple DMA,Added interrupt support for Zynq.
// * 4.00a srt  08/04/11 Changed a typo in the RxIntrHandler, changed
// *		       XAXIDMA_DMA_TO_DEVICE to XAXIDMA_DEVICE_TO_DMA
// * 5.00a srt  03/06/12 Added Flushing and Invalidation of Caches to fix CRs
// *		       648103, 648701.
// *		       Added V7 DDR Base Address to fix CR 649405.
// * 6.00a srt  03/27/12 Changed API calls to support MCDMA driver.
// * 7.00a srt  06/18/12 API calls are reverted back for backward compatibility.
// * 7.01a srt  11/02/12 Buffer sizes (Tx and Rx) are modified to meet maximum
// *		       DDR memory limit of the h/w system built with Area mode
// * 7.02a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
// * 9.1   adk  01/07/16 Updated DDR base address for Ultrascale (CR 799532) and
// *		       removed the defines for S6/V6.
// * 9.2   vak  15/04/16 Fixed compilation warnings in the example
// * 9.3   ms   01/23/17 Modified xil_printf statement in main function to
// *                     ensure that "Successfully ran" and "Failed" strings are
// *                     available in all examples. This is a fix for CR-965028.
// * 9.6   rsp  02/14/18 Support data buffers above 4GB.Use UINTPTR for typecasting
// *                     buffer address (CR-992638).
// * 9.9   rsp  01/21/19 Fix use of #elif check in deriving DDR_BASE_ADDR.
// * </pre>
// *
// * ***************************************************************************
// */
//
///***************************** Include Files *********************************/
//
//
//#include "xaxidma.h"
//#include "xparameters.h"
//#include "xil_exception.h"
//#include "xdebug.h"
//
//#ifdef XPAR_UARTNS550_0_BASEADDR
//#include "xuartns550_l.h"       /* to use uartns550 */
//#endif
//
//
//#ifdef XPAR_INTC_0_DEVICE_ID
// #include "xintc.h"
//#else
// #include "xscugic.h"
//#endif
//
///************************** Constant Definitions *****************************/
//
///*
// * Device hardware build related constants.
// */
//
//#define DMA_DEV_ID		XPAR_AXIDMA_0_DEVICE_ID
//#define DMA_DEV_ID2		XPAR_AXIDMA_1_DEVICE_ID
//
//#ifdef XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
//#define DDR_BASE_ADDR		XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
//#elif defined (XPAR_MIG7SERIES_0_BASEADDR)
//#define DDR_BASE_ADDR	XPAR_MIG7SERIES_0_BASEADDR
//#elif defined (XPAR_MIG_0_BASEADDR)
//#define DDR_BASE_ADDR	XPAR_MIG_0_BASEADDR
//#elif defined (XPAR_PSU_DDR_0_S_AXI_BASEADDR)
//#define DDR_BASE_ADDR	XPAR_PSU_DDR_0_S_AXI_BASEADDR
//#endif
//
//#ifndef DDR_BASE_ADDR
//#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
//		DEFAULT SET TO 0x01000000
//#define MEM_BASE_ADDR		0x01000000
//#else
//#define MEM_BASE_ADDR		(DDR_BASE_ADDR + 0x1000000)
//#endif
//
//#ifdef XPAR_INTC_0_DEVICE_ID
//#define RX_INTR_ID		XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID
//#define TX_INTR_ID		XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID
//
//#define RX_INTR_ID2		XPAR_INTC_0_AXIDMA_1_S2MM_INTROUT_VEC_ID
//#define TX_INTR_ID2		XPAR_INTC_0_AXIDMA_1_MM2S_INTROUT_VEC_ID
//#else
//#define RX_INTR_ID		XPAR_FABRIC_AXIDMA_0_S2MM_INTROUT_VEC_ID
//#define TX_INTR_ID		XPAR_FABRIC_AXIDMA_0_MM2S_INTROUT_VEC_ID
//#endif
//
//#define TX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00100000)
//#define RX_BUFFER_BASE		(MEM_BASE_ADDR + 0x00300000)
//#define RX_BUFFER_HIGH		(MEM_BASE_ADDR + 0x004FFFFF)
//
//
//#ifdef XPAR_INTC_0_DEVICE_ID
//#define INTC_DEVICE_ID          XPAR_INTC_0_DEVICE_ID
//#else
//#define INTC_DEVICE_ID          XPAR_SCUGIC_SINGLE_DEVICE_ID
//#endif
//
//#ifdef XPAR_INTC_0_DEVICE_ID
//#define INTC		XIntc
//#define INTC_HANDLER	XIntc_InterruptHandler
//#else
// #define INTC		XScuGic
// #define INTC_HANDLER	XScuGic_InterruptHandler
//#endif
//
//
///* Timeout loop counter for reset
// */
//#define RESET_TIMEOUT_COUNTER	10000
//
//#define TEST_START_VALUE	0xC
///*
// * Buffer and Buffer Descriptor related constant definition
// */
////#define MAX_PKT_LEN		0x100
//#define MAX_PKT_LEN			6196		//0x1834
//
//#define NUMBER_OF_TRANSFERS	10
//
///* The interrupt coalescing threshold and delay timer threshold
// * Valid range is 1 to 255
// *
// * We set the coalescing threshold to be the total number of packets.
// * The receive side will only get one completion interrupt for this example.
// */
//
///**************************** Type Definitions *******************************/
//
//
///***************** Macros (Inline Functions) Definitions *********************/
//
//
///************************** Function Prototypes ******************************/
//#ifndef DEBUG
//extern void xil_printf(const char *format, ...);
//#endif
//
//#ifdef XPAR_UARTNS550_0_BASEADDR
//static void Uart550_Setup(void);
//#endif
//
//u8 *CmdTxBufferPtr;
//u8 *CmdRxBufferPtr;
//
//u8 *CmdRxBufferPtr_1x;
//
//int Simple1xDmaInit();
//int CheckData(int Length, u8 StartValue);
//void TxIntrHandler(void *Callback);
//void RxIntrHandler(void *Callback);
//
//
//
//
////int SetupIntrSystem(INTC * IntcInstancePtr,
////			   XAxiDma * AxiDmaPtr, u16 TxIntrId, u16 RxIntrId,XAxiDma * AxiDmaPtr1, u16 TxIntrId1, u16 RxIntrId1);
//int SetupIntrSystem(INTC * IntcInstancePtr,
//			   XAxiDma * AxiDmaPtr, u16 TxIntrId, u16 RxIntrId);
//int SetupIntrSystem1(INTC * IntcInstancePtr,
//			   XAxiDma * AxiDmaPtr, u16 TxIntrId, u16 RxIntrId);
//
//void DisableIntrSystem(INTC * IntcInstancePtr,
//					u16 TxIntrId, u16 RxIntrId);
//
//
//
///************************** Variable Definitions *****************************/
///*
// * Device instance definitions
// */
//
//
//XAxiDma AxiDma;		/* Instance of the XAxiDma */  //1x dma
//XAxiDma AxiDma1; 								   //tcp dma
//
//
////static INTC Intc;	/* Instance of the Interrupt Controller */
//extern INTC Intc;	/* Instance of the Interrupt Controller */
///*
// * Flags interrupt handlers use to notify the application context the events.
// */
//volatile int TxDone;
//volatile int RxDone;
//volatile int Error;
//
///*****************************************************************************/
///**
//*
//* Main function
//*
//* This function is the main entry of the interrupt test. It does the following:
//*	Set up the output terminal if UART16550 is in the hardware build
//*	Initialize the DMA engine
//*	Set up Tx and Rx channels
//*	Set up the interrupt system for the Tx and Rx interrupts
//*	Submit a transfer
//*	Wait for the transfer to finish
//*	Check transfer status
//*	Disable Tx and Rx interrupts
//*	Print test status and exit
//*
//* @param	None
//*
//* @return
//*		- XST_SUCCESS if example finishes successfully
//*		- XST_FAILURE if example fails.
//*
//* @note		None.
//*
//******************************************************************************/
//
//#endif
//
//
//
